The present invention relates to chemical mechanical planarization (“CMP”) polishing compositions (CMP slurries, CMP composition or CMP formulations are used interchangeably) used in the production of a semiconductor device, and polishing methods for carrying out chemical mechanical planarization. In particular, it relates to polishing compositions comprising composite abrasive particles that are suitably used for polishing patterned semiconductor wafers that composed of oxide materials.
Silicon oxide is widely used as dielectric materials in semiconductor industry. There are several CMP steps in integrated circuit (IC) manufacturing process, such as shallow trench isolation (STI), inter-layer dielectric (ILD) CMP and gate poly CMP etc. Typical oxide CMP slurry involves: abrasive, with or without other chemicals. Other chemicals could be dispersants to improve slurry stability, booster to increase removal rate, or inhibitors to decrease removal rate and to stop on the other film, for example, SiN for STI application.
Among common abrasives used in CMP slurries, such as silica, alumina, zirconia, titania and so on, ceria is well-known for its high reactivity toward silica oxide and is widely used in STI CMP slurry for the highest oxide removal rate (RR) due to the high reactivity of ceria to silica.
Cook et al. (Lee M. Cook, Journal of Non-Crystalline Solids 120 (1990) 152-171) proposed a ‘chemical tooth’ mechanism to explain this extraordinary property of ceria. According to this mechanism, when ceria particles are pressed onto silicon oxide film, ceria breaks down silica bonds, forms a Ce—O—Si structure and thus cleavage silica from the surface.
As the semiconductor technology has evolved, there are a number of new applications that demand innovative CMP solutions to meet requirements of high silicon oxide removal rates and a high degree of planarity. One of such applications is in manufacturing three-dimensional (3D) memory structures. 3D memory structures stacks the memory cells vertically allowing a wider gap between each cell, overcoming the patterning restrictions. 3D NAND typically uses alternating layers of thick (height) oxides and nitride or oxide and conductor layers to form vertical NAND structures in the form of a staircase. Oxide layers are typically thicker (have a height greater) than 1 micron or 2 microns or 3 microns. In order to maintain throughput requirements, oxide layers need to be polished at very high rates, stop on the optional second film or stopping layer (located beneath the oxide layer) such as nitride or poly-Si layer and cause minimal dishing of the oxide trench structures. Many of the high rate oxide CMP slurries available in the market cause a dome-like topography during polishing. The dome or rounded features are formed of residual oxide in the oxide regions (active oxide regions) surrounding the trenches while polishing thick and wide oxide structures. It is important to minimize rounding of large oxide structures (thereby forming the dome-like topography) to minimize oxide loss in trenches and prevent complete loss of stopping layer in the areas adjacent to the trenches.
Therefore, there are significant needs for CMP compositions, methods, and systems that can offer higher removal rate of silicon oxide and high planarization efficiency, without forming the dome-like topography. Slurries should also have excellent stopping ability on silicon nitride or poly-Si films and provide low oxide loss for wide trench structures.